1. Field of the Invention
The present invention relates to an analog-digital converter for converting an analog signal to a digital signal.
2. Description of the Prior Art
The technique of forming lines adjacent to each other within one interconnect layer and using fringing capacitance between these lines has been known in order to obtain large capacitance while decreasing an area consumed by a capacitor over a semiconductor substrate (see, for example, Japanese Laid-Open Patent Publication No. 61-263251 and Japanese Patent No. 2700959).
An analog-digital converter including the above-mentioned capacitor has a capacitor array block 902 in which unit capacitors 901 having a predetermined capacitance are densely situated in the row and column direction as shown in, for example, FIG. 1. The capacitor array block 902 is surrounded by a dummy capacitor 903 in order to reduce variations in the capacitance of each unit capacitor 901.
The unit capacitors 901 are organized into groups, which consist of predetermined numbers (for example 16, 8, 4, 2, and 1) of unit capacitors 901, and these groups of unit capacitors 901 are respectively connected to corresponding discrete lines (16C_Lin, 8C_Lin, 4C_Lin, 2C_Lin, and 1C_Lin_a to 1C_Lin_f) at the electrodes on one side. Each discrete line is connected to an analog switch 904a in a voltage switching circuit 904 situated near the capacitor array block 902. Predetermined reference voltages, the predetermined reference voltages divided by an R-2R resistance array 905, or analog input voltages are selectively applied to each discrete line.
The unit capacitors 901 are connected to a comparator 906 via a common line (com_Lin) at the electrodes on the other side. An output of the comparator 906 is input to a control circuit 907 and converted to, for example, 10-bit digital values D0-D9.
As an example of other techniques for a circuit having a transistor and a capacitor, a technique has been known in which a line having the same pattern as each of electrodes is aligned over each of the electrodes so as to form a capacitor to be connected between a source region and a drain region, such as a transistor of a power amplifier (see the specification of U.S. Pat. No. 6,747,307).
In the above-mentioned analog-digital converter having the voltage switching circuit 904 situated near the capacitor array block 902, the fringing capacitance is advantageously used, so that it is possible to decrease the area consumed by the capacitor array block 902. However, it is not possible for the above-mentioned analog-digital converter to reduce an area consumed by the voltage switching circuit 904. Therefore, overall area miniaturization of the analog-digital converter is difficult.
The groups of the unit capacitors 901 have different discrete line layouts. Beside that, it is difficult to avoid (i) crossovers of discrete lines and (ii) crossovers of discrete lines and the common line. For these reasons, it difficult to achieve high accuracy in relative capacitance ratio in each group and to decrease effects of cross-talk. Therefore, obtaining a highly accurate analog-digital converter is difficult.
Moreover, in the arrangement in which the capacitor is formed by aligning lines over the source region and over the drain region of the transistor, it is not possible to arbitrary select a polarity of transistor and design a connection relationship between the transistor and the capacitor. Moreover, the position of each electrode is determined by the size or shape of the transistor. Therefore, desired capacitance is not necessarily obtained.